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62 lines
1.5 KiB
Plaintext
62 lines
1.5 KiB
Plaintext
6 months ago
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<?xml version="1.0" encoding="utf-8"?>
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<TcPlcObject Version="1.1.0.1" ProductVersion="3.1.4024.12">
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<POU Name="CLK_PRG" Id="{5c80c50e-5dd2-42bd-9374-17f4b5709650}" SpecialFunc="None">
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<Declaration><![CDATA[FUNCTION_BLOCK CLK_PRG
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VAR_INPUT
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PT : TIME := t#10ms;
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END_VAR
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VAR_OUTPUT
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Q : BOOL;
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END_VAR
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VAR
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init : BOOL;
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last : TIME;
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tx: TIME;
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END_VAR]]></Declaration>
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<Implementation>
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<ST><![CDATA[(*
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version 1.3 25. oct. 2008
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programmer hugo
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tested by tobias
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clk_prg uses the internal sps time to generate a clock with programmable period time.
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the first cycle after start is a clk pulse and then depending on the programmed period time a delay.
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every pulse is only valid for one cycle.
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the accuracy of clk_prg is depending on the accuracy of the system clock.
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*)
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(* @END_DECLARATION := '0' *)
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(* read system time *)
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tx := DWORD_TO_TIME(T_PLC_MS());
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(* initialize on startup *)
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IF NOT init THEN
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init := TRUE;
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last := tx - pt;
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END_IF;
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(* generate output pulse when next_pulse is reached *)
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Q := tx - last >= pt;
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IF Q THEN last := tx; END_IF;
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(* revision hiostory
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hm 25 feb 2007 rev 1.1
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rewritten code for higher performance
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pt can now be changed during runtime
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hm 17. sep 2007 rev 1.2
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replaced time() with t_plc_ms() for compatibility reasons
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hm 25. oct. 2008 rev 1.3
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optimized code
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*)]]></ST>
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</Implementation>
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<LineIds Name="CLK_PRG">
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<LineId Id="20" Count="37" />
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<LineId Id="9" Count="0" />
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</LineIds>
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</POU>
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</TcPlcObject>
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